In a system having a plurality of subsystems which are functionally integrated via an asynchronously operating bus, a need for data coherency arises. In such a system a bus controller normally communicates with up to a certain number of remote terminal interfaces which individually interface the bus with a related subsystem. For example, in a MIL-STD-1553 context, the bus controller can communicate with up to 31 remote terminal interfaces. All of the remote terminal interfaces (RTI's) are capable of communicating with one other at the behest of the bus controller. There is a potential problem in such a system of the subsystems' CPUs obtaining incoherent data blocks or messages. A coherent message is one in which the data or parameters refer to a unique computation performed on a unique data set and belonging to a unique time frame. Incoherency involves the transmission and/or use of partial, i.e., incoherent messages made up of data belonging to different time frames, computations, or data sets. For example, an RTI can receive a message consisting of many words from the bus, can store that message, and can begin to overwrite or update the stored information while the host CPU is still in the process of reading the previously written message. In other words, the RTI is updated in midstream with new information before the old information can be transferred completely to the CPU. Thus, the CPU can receive, for example, the first half of the message from one time frame while the second half of the message is from a different time frame. If the bus is used for interfacing with critical avionics subsystems, where highly accurate and coherent information is critical, such incoherency can have disastrous consequences.
One of the prior art methods of attacking this problem is to create a double buffering type situation in which the messages received are alternately placed in one of two memory buffers. While a first message is occupying the first memory buffer a second message can be received in the second memory buffer. Thus a small amount of time is sacrificed for ensuring coherency. However, if a burst of information is transmitted on the asynchronous bus to the particular RTI, the double buffering solution may not be successful in retaining all the transmitted information. If the CPU can respond in a timely manner, this method can ensure coherency. However, in the majority of high performance subsystems communicating with a bus, the CPU is quite busy performing other tasks and cannot respond to a burst of messages or block transmissions using the same message label. Thus, some data will be lost if the transfer rate is greater than the rate of acceptance capabilities of the double buffering architecture. Of course, it is conceivable that a system designer could set up a triple, quadruple, quintuple, or any number of buffering architectures. However, this would be extremely expensive because of: (a) the necessity of designing each buffer in such a way that it can accept a full block (there are 32 words in MIL-STD-1553B block) thus ensuring considerable waste of memory for messages containing less than the full number of words for a block; (b) the need for updating, in a rapid and orderly manner, the "addresses" of the last "tenants" of the first buffer each time a new message is received into the first buffer; (c) the buffering type solution requires a great deal of hardware and CPU throughput; and, (d) the need for interrupting the CPU everytime new information is shifted into the last available buffer.
A second level of coherency problems exists in the prior art. Each data word within a message belongs to a unique time frame. However, if two or more messages are received by the RTI at different times but are buffered and read out by the host CPU at the same time, the problem of time consistency between such critical messages arises.
Both of the above described first and second levels of coherency problems have been addressed in said commonly owned copending applications entitled COHERENT INTERFACE WITH WRAPAROUND RECEIVE MEMORY and COHERENT INTERFACE WITH WRAPAROUND RECEIVE AND TRANSMIT MEMORIES.
A third level of coherency problems exists in the prior art. It is the problem of efficiently transferring data between one or more simplex busses such as MIL-STD-1553 and one or more subsystems, typically a set of redundant synchronous subsystems. In general, a simplex bus can communicate with only one channel at any given time. Under MIL-STD-1553, each subsystem is provided a unique terminal address on the bus. The electrical and operational characteristics of this interface do not permit a variable number of redundant channels to receive and transmit data to and from the bus using the same RTI address. Therefore, in a redundant subsystem with one RTI with one RTI address the bus can be connected to one and only one redundant channel at any time and the data must be internally distributed and coherently used by the other redundant channels. This requires that the channel receiving the bus messages must transmit the data to all redundant channels in an efficient manner over interchannel links. These links are generally used for other data as well and as such the bandwidths of these links is usually limited.
Thus an inexpensive and simple means of insuring data coherency and time consistency for redundant synchronous subsystems is desirable.